1. Field of the Invention
The present invention relates to trace formation in the fabrication of semiconductor devices. More particularly, the present invention relates to the formation of routing traces on an external surface of a semiconductor device.
2. State of the Art
Integrated circuit ("IC") devices generally consist of a plurality of components (such as resistors, capacitors, diodes, transistors, fuses, conductors, and the like) fabricated on a single semiconductor chip. Each of these components is electrically isolated from one another by dielectric materials. Thus, in order to interact with one another to form an integrated circuit, a plurality conductive interconnections (hereinafter "traces") must be formed between the components.
FIG. 10 illustrates an exemplary trace configuration connecting a pair of pinch resistors 202 and 204 in series in an IC device. First and second pinch resistors 202 and 204, respectively, are formed in a p-type substrate 206 by doping n-type regions 208 and 212, respectively, into the p-type substrate 206. P-type regions 214 and 216, respectively, are doped into the n-type regions 208 and 212 to reduce the cross-sectional area of the resistor, thereby increasing its respective resistance. A first trace 218 is disposed atop a dielectric layer 222 and routes an electric current to the first pinch resistor 202 through a first contact 224 through the dielectric layer 222. The electric current travels through the first pinch resistor 202 and through a second contact 226 through the dielectric layer 222. A second trace 228 is disposed atop the dielectric layer 222 and is in electrical contact with the second contact 226. The second trace 228 routes the electric current to the second pinch resistor 204 by a third contact 232 through the dielectric layer 222. The electric current travels through the second pinch resistor 204 and exits through a fourth contact 234 through the dielectric layer 222. A third trace 236 is disposed atop the dielectric layer 222 and is in electrical contact with the fourth contact 234 to route the electric current to other components in the IC device.
Higher performance, lower cost, increased miniaturization of the components comprising the IC devices, and greater packaging density of IC devices are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, IC devices have been continually redesigned to achieved ever-higher degrees of integration which has reduced the size of the IC device. However, as the dimensions of the IC devices are reduced, the geometry of the components and circuit elements has also decreased. Moreover, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry traces, contacts, dielectric thickness, and the like) become more and more stringent. Although the reduction in size creates technical problems, the future advancement of the technology requires such size reductions.
Of course, the reduction in component size and density packing (smaller component-to-component spacing) of the components in the IC devices has resulted in a greatly reduced area for running traces to interconnect the components. Furthermore, the integration and densification process in IC devices has caused the continuous migration of traces and connections, which were previously routed on printed circuit boards, cards, and modules, to the IC device itself, yet further reducing potential area for forming traces. Thus, multilevel metallization has become a technique to cope with the reduced area. Multilevel metallization is a technique of forming traces on different layers of dielectric material over the components. FIG. 11 illustrates an exemplary four-tier metallizaton structure 240. The metallization structure 240 shows an active area 242 formed in a semiconductor substrate 244 which is in electrical communication with a first level trace 246, such as aluminum, tungsten, titanium, or various alloys thereof. The first level trace 246 is disposed over a first level barrier layer 248, such as a silicon nitride layer, which is over the semiconductor substrate 244. A first level dielectric layer 252 is disposed over the first level trace 246 and the exposed first level barrier layer 248. A second level barrier layer 254 is disposed over the first level dielectric layer 252 and a second level trace 256 is formed on the second level barrier layer 254. The first level trace 246 and the second level trace 256 are in electrical communication through a first-to-second level contact 258 which extends through the first level dielectric layer 252 and the second level barrier layer 254.
A second level dielectric layer 262 is disposed over the second level trace 256 and the exposed second level barrier layer 254. A third level barrier layer 264 is disposed over the second level dielectric layer 262 and a third level trace 266 is formed on the third level barrier layer 264. The second level trace 256 and the third level trace 266 are in electrical communication through a second-to-third level contact 268 which extends through the second level dielectric layer 262 and the third level barrier layer 264.
A third level dielectric layer 272 is disposed over the third level trace 266 and the exposed third level barrier layer 264. A fourth level barrier layer 274 is disposed over the third level dielectric layer 272 and a fourth level trace 276 is formed on the fourth level barrier layer 274. The third level trace 266 and the fourth level trace 276 are in electrical communication through a third-to-fourth level contact 278 which extends through the third level dielectric layer 272 and the fourth level barrier layer 274.
A fourth level dielectric layer 282 is disposed over the fourth level trace 276 and the exposed fourth level barrier layer 274. The upper surface 284 of the fourth level dielectric layer 282 is used to form bond pads 286 in specific locations and external communication traces 288 conduct input/output signals to solder balls 292. The solder balls 292 will be connected to external devices, such as a printed circuit board, to relay input/output signals therebetween.
FIG. 12 is a top view of the metallization structure 240 of FIG. 11 prior to the addition of solder balls 292. As FIG. 12 illustrates, the bond pads 286 are patterned in specific locations for active surface-down mounting to contact sites of metal conductors of a carrier substrate (not shown), such as a printed circuit board, FR4, or the like, wherein the contact sites are a mirror-image of the bond pads 286 pattern on the metallization structure 240. It is, of course, understood that although the bond pads 286 are illustrated as substantially square, they can be of any shape, including round, as shown as round bond pad 294.
Although multilayer metallization is effective in compensating for reduced areas for trace patterning, the thickness of the IC device is also a concern. Therefore, it can be appreciated that it would be advantageous to develop a technique which would maximize the available area on an IC device for patterning traces for the interconnection of IC device components, without adding additional layers to the multilayer structure.